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Quad-Channel Isolator with Integrated DC-to-DC Converter
Preliminary Technical Data
FEATURES
isoPower integrated, isolated dc-to-dc converter Regulated 3.3 V or 5 V output 500 mW output power Quad dc-to-25 Mbps (NRZ) signal isolation channels Schmitt trigger inputs 16-lead SOIC package with >8 mm creepage High temperature operation: 105C High common-mode transient immunity: >25 kV/s Safety and regulatory approvals (pending) UL recognition 2500 V rms for 1 minute per UL1577 CSA Component Acceptance Notice #5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak
ADuM5400
FUNCTIONAL BLOCK DIAGRAMS
Figure 1.
APPLICATIONS
RS-232/RS-422/RS-485 transceiver Industrial field bus isolation Power supply startup bias and gate drive Isolated sensor interface Industrial PLC
Figure 2. ADuM5400
GENERAL DESCRIPTION
The ADuM54001 device is a quad-channel digital isolators with isoPowerTM, an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler(R) technology, the dc-to-dc converter provides up to 500 mW of regulated, isolated power at either 5.0 V from a 5.0 V input supply or 3.3 V from a 3.3 V supply. This eliminates the need for a separate, isolated dc-to-dc converter in low power, isolated designs. The iCoupler chip scale transformer technology is used to isolate the logic signals and the magnetic components of the dc-to-dc converter. The result is a small form factor, total isolation solution. The ADuM5400 isolator provides four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for more information).
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7075 329 B2. Other patents pending.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADuM5400
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics--5 V Primary Input Supply/ 5 V Secondary Isolated Supply ................................................... 3 Electrical Characteristics--3.3 V Primary Input Supply/ 3.3 V Secondary Isolated Supply ................................................ 5 Package Characteristics ............................................................... 7 Regulatory Approvals................................................................... 7 Insulation and Safety-Related Specifications............................ 7 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics............................................................ 8 Recommended Operating Conditions ...................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9
Preliminary Technical Data
Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 13 Applications Information .............................................................. 14 Theory of Operation .................................................................. 14 PC Board Layout ........................................................................ 14 Thermal Analysis ....................................................................... 14 Propagation Delay-Related Parameters................................... 15 EMI Considerations................................................................... 15 DC Correctness and Magnetic Field Immunity........................... 15 Power Consumption .................................................................. 16 Power Considerations................................................................ 17 Insulation Lifetime ..................................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
Rev. PrA | Page 2 of 21
Preliminary Technical Data SPECIFICATIONS
ADuM5400
ELECTRICAL CHARACTERISTICS--5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V VDD1 5.5 V, VSEL = VISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = 5.0 V, VSEL = VISO = 5.0 V. Table 1.
Parameter DC-TO-DC CONVERTER POWER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Pulse-Width Modulation Frequency iCoupler DATA CHANNELS DC to 2 Mbps Data Rate1 Maximum Output Supply Current2 Efficiency at Maximum Output Supply Current3 IDD1 Supply Current, No VISO Load 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load ADuM5400 Available VISO Supply Current4 ADuM5400 IDD1 Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold Symbol VISO VISO(LINE) VISO(LOAD) VISO(RIP) VISO(N) fOSC fPWM Min 4.7 Typ 5.0 1 1 75 200 180 625 Max 5.4 5 Unit V mV/V % mV p-p mV p-p MHz kHz Test Conditions/Comments IISO = 0 mA IISO = 50 mA, VDD1 = 4.5 V to 5.5 V IISO = 10 mA to 90 mA 20 MHz bandwidth, CBO = 0.1 F10 F, IISO = 90 mA 20 MHz bandwidth, CBO = 0.1 F10 F, IISO = 90 mA
IISO(MAX)
100 34
mA % 30 mA
f 1 MHz, VISO > 4.5 V IISO = IISO(2,MAX), f 1 MHz IISO = 0 mA, f 1 MHz
IDD1(Q) IDD1(D)
19
64 IISO(LOAD) IDD1(MAX) IIA, IIB, IIC, IID VIH VIL 89 290 +0.01
mA mA mA A V V
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD = 5 V, IISO = 100 mA
-20 0.7 x VISO, 0.7 x VIDD1
+20
0.3 x VISO, 0.3 x VIDD1 VDD1 - 0.3, VISO - 0.3 VDD1 - 0.5, VISO - 0.3 5.0 4.8 0.0 0.0 0.1 0.4
Logic High Output Voltages
VOAH, VOBH, VOCH, VODH
V V V V
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL, VOCL, VODL
AC SPECIFICATIONS ADuM5400ARWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM5400CRWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching,
PW 1 tPHL, tPLH PWD tPSK tPSKCD/tPSKOD PW 25 tPHL, tPLH PWD tPSK tPSKCD 45 5 55
1000 100 40 50 50 40 60 6 15 6
Rev. PrA | Page 3 of 21
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
ADuM5400
Parameter Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Preliminary Technical Data
Symbol tPSKOD tR/tF |CMH| |CML| fr 2.5 35 35 1.0 Min Typ Max 15 Unit ns ns kV/s kV/s Mbps Test Conditions/Comments CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
25 25
The contributions of supply current values for all four channels are combined at identical data rates. The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
Rev. PrA | Page 4 of 21
Preliminary Technical Data
ADuM5400
ELECTRICAL CHARACTERISTICS--3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V VDD1 3.6 V, VSEL = GNDISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = 3.3 V, VISO = 3.3 V, VSEL = GNDISO. Table 2.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Pulse-Width Modulation Frequency iCoupler DATA CHANNELS DC to 2 Mbps Data Rate1 Maximum Output Supply Current2 Efficiency at Maximum Output Supply Current3 IDD1 Supply Current, No VISO Load 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load ADuM5400 Available VISO Supply Current4 ADuM5400 IDD1 Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages
Symbol
VISO VISO(LINE) VISO(LOAD) VISO(RIP) VISO(N) fOSC fPWM
Min
3.0
Typ
3.3 1 1 50 130 180 625
Max
3.6 5
Unit
V mV/V % mV p-p mV p-p MHz kHz
Test Conditions/Comments
IISO = 0 mA IISO = 37.5 mA, VDD1 = 3.0 V to 3.6 V IISO = 6 mA to 54 mA 20 MHz bandwidth, CBO = 0.1 F10 F, IISO = 54 mA 20 MHz bandwidth, CBO = 0.1 F10 F, IISO = 54 mA
IISO(MAX)
60 36
mA % 20 mA
f 1 MHz, VISO > 3.0 V IISO = IISO(2,max), f 1 MHz IISO = 0 mA, f 1 MHz
IDD1(Q) IDD1(D)
14
41 IISO(LOAD) IDD1(MAX) IIA, IIB, IIC, IID VIH VIL VOAH, VOBH, VOCH, VODH VDD1 - 0.2, VISO - 0.2 VDD1 - 0.5, V1SO - 0.5 5.0 4.8 0.0 0.0 0.1 0.4 43 175 +0.01
mA mA mA A V V V V V V
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD = 3.3 V, IISO = 60 mA
-10 0.7 x VISO, 0.7 x VIDD1
+10
0.3 x VISO, 0.3 x VIDD1
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL, VOCL, VODL
AC SPECIFICATIONS ADuM5400ARWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM5400CRWZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels
PW 1 tPHL, tPLH PWD tPSK tPSKCD/tPSKOD PW 25 tPHL, tPLH PWD tPSK tPSKCD
Rev. PrA | Page 5 of 21
1000 60 100 40 50 50 40 45 5 45 6 60 6
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
ADuM5400
Parameter
Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Preliminary Technical Data
Symbol
tPSKOD tR/tF |CMH| |CML| fr 2.5 35 35 1.0
Min
Typ
Max
15
Unit
ns ns kV/s kV/s Mbps
Test Conditions/Comments
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
25 25
The contributions of supply current values for all four channels are combined at identical data rates. The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
Rev. PrA | Page 6 of 21
Preliminary Technical Data
PACKAGE CHARACTERISTICS
Table 3.
Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Input Capacitance2 IC Junction to Ambient Thermal Resistance
1 2
ADuM5400
Min Typ 1012 2.2 4.0 45 Max Unit pF pF C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside, test conducted on four-layer board with thin traces.3
Symbol RI-O CI-O CI JA
The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together; and Pin 9 to Pin 16 are shorted together. Input capacitance is from any input data pin to ground. 3 See the Thermal Analysis section for thermal model definitions.
REGULATORY APPROVALS
Table 4.
UL (Pending) Recognized under the UL1577 component recognition program1 Reinforced insulation, 2500 V rms isolation voltage File E214100
1 2
CSA (Pending) Approved under CSA Component Acceptance Notice #5A Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 300 V rms (424 V peak) maximum working voltage File 205078
VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL1577, each ADuM5400 is proof tested by applying an insulation test voltage of 3000 V rms for 1 sec (current leakage detection limit = 10 A). In accordance with DIN V VDE V 0884-10, each of the ADuM5400 is proof tested by applying an insulation test voltage of 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Symbol L(I01) L(I02) Value 2500 >8.0 >8.0 Unit V rms mm mm Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group
0.017 min mm >175 V IIIa
Rev. PrA | Page 7 of 21
ADuM5400
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
Preliminary Technical Data
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 6.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS
600
Conditions
Symbol
Characteristic I to IV I to III I to II 40/105/21 2 560 1050
Unit
VIORM x 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM x 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM x 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 3)
VIORM VPR VPR
V peak V peak
896 672 VTR 4000
V peak V peak V peak
VIO = 500 V
TS IS1 IS2 RS
150 265 335 >109
C mA mA
SAFE OPERATING VDD1 CURRENT (mA)
500
400
300
200
100
0
0
50 100 150 AMBIENT TEMPERATURE (C)
200
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 7.
Parameter Operating Temperature Supply Voltages1 VDD1 @ VSEL = 0 V VDD1 @ VSEL = 5 V Minimum Load
1
Symbol TA VDD VDD IISO(MIN)
Min -40 3.0 4.5 10
06577-002
Max +105 3.6 5.5
Unit C V V mA
All voltages are relative to their respective ground.
Rev. PrA | Page 8 of 21
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25C, unless otherwise noted. Table 8.
Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VDD, VISO)1 Input Voltage (VIA, VIB, VIC, VID, VSEL)1, 2 Output Voltage (VOA, VOB, VOC, VOD)1, 2 Average Output Current per Pin3 Side 1 (IO1) Side 2 (IOISO) Common-Mode Transients4
1 2
ADuM5400
Rating -55C to +150C -40C to +105C -0.5 V to +7.0 V -0.5 V to VDDI + 0.5 V -0.5 V to VDDO + 0.5 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
-18 mA to +18 mA -22 mA to +22 mA -100 kV/s to +100 kV/s
All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 3 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.
Table 9. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1
Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation
1
Max 424 600 560 600 560
Unit V peak V peak V peak V peak V peak
Applicable Certification All certifications Working voltage per IEC 60950-1 Working voltage per VDE V 0884-10 Working voltage per IEC 60950-1 Working voltage per VDE V 0884-10
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Table 10. Truth Table (Positive Logic)
VIx Input1 High Low High Low High Low High Low
1
VSEL Input High High Low Low Low Low High High
VDD1 State Powered Powered Powered Powered Powered Powered Powered Powered
VDD1 Input (V) 5.0 5.0 3.3 3.3 5.0 5.0 3.3 3.3
VISO State Powered Powered Powered Powered Powered Powered Powered Powered
VISO Output (V) 5.0 5.0 3.3 3.3 3.3 3.3 5.0 5.0
VOx Output1 High Low High Low High Low High Low
Notes Normal operation, data is high Normal operation, data is low Normal operation, data is high Normal operation, data is low Configuration not recommended Configuration not recommended Configuration not recommended Configuration not recommended
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
Rev. PrA | Page 9 of 21
ADuM5400
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
Figure 4. ADuM5400 Pin Configuration
Table 11. ADuM5400 Pin Function Descriptions
Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V. 2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 VID Logic Input D. 7 NC Make no connection to this pin. 9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. VDD1 and VISO voltages must be in the same operating range to guarantee proper operation of the data channels. 11 VOD Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High). VDD1 and VISO voltages must be in the same operating range to guarantee proper operation of the data channels.
Rev. PrA | Page 10 of 21
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
40 35 30
4.0 3.5 3.0 2.5 2.0 1.5 1.0
INPUT CURRENT (A) AND POWER (W)
ADuM5400
POWER
EFFICIENCY (%)
25 20 15 10 5 0
06577-008
3.3V IN/3.3V OUT 5V IN/5V OUT
IDD 0.5 0 3.0
0
0.02
0.04 0.06 0.08 OUTPUT CURRENT (A)
0.10
0.12
3.5
4.0
4.5
5.0
5.5
6.0
6.5
INPUT VOLTAGE (V)
Figure 5. Typical Power Supply Efficiency at 5 V/5 V and 3.3 V/3.3 V
1.0 0.9 0.8
POWER DISSIPATION (W)
Figure 8. Typical Short-Circuit Input Current and Power vs. VDD Supply Voltage
0.7 0.6 0.5
OUTPUT VOLTAGE (500mV/DIV)
10% LOAD
90% LOAD
0.4 0.3 0.2 0.1
06577-009
VDD1 = 5V, VISO = 5V VDD1 = 3.3V, VISO = 3.3V
DYNAMIC LOAD
0 0 0.02 0.04 0.06 0.08 0.10 0.12
(100s/DIV)
IISO (A)
Figure 6. Typical Total Power Dissipation vs. IISO with Data Channels Idle
0.12
Figure 9. Typical VISO Transient Load Response, 5 V Output, 10% to 90% Load Step
OUTPUT VOLTAGE (500mV/DIV)
0.10
OUTPUT CURRENT (A)
0.08
0.06
DYNAMIC LOAD
0.04 3.3V IN/3.3V OUT 5V IN/5V OUT 0.02
10% LOAD
90% LOAD
06577-010
0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
(100s/DIV)
INPUT CURRENT (A)
Figure 7. Typical Isolated Output Supply Current, IISO, as a Function of External Load, No Dynamic Current Draw at 5 V/5 V and 3.3 V/3.3 V
Figure 10. Typical Transient Load Response, 3 V Output, 10% to 90% Load Step
Rev. PrA | Page 11 of 21
06577-013
06577-012
06577-011
ADuM5400
20
5V OUTPUT RIPPLE (10mV/DIV)
Preliminary Technical Data
5V IN/5V OUT 3.3V IN/3.3V OUT
16
SUPPLY CURRENT (mA)
06577-014
12
8
4
BW = 20MHz (400ns/DIV)
0
5
10 15 DATA RATE (Mbps)
20
25
Figure 11. Typical VISO = 5 V Output Voltage Ripple at 90% Load
Figure 14. Typical ICH Supply Current per Reverse Data Channel (15 pF Output Load)
5
3.3V OUTPUT RIPPLE (10mV/DIV)
4
SUPPLY CURRENT (mA)
3
5V
2
3.3V
1
06577-015
0
5
BW = 20MHz (400ns/DIV)
10 15 DATA RATE (Mbps)
20
25
Figure 12. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load
Figure 15. Typical IISO(D) Dynamic Supply Current per Input
20
5V IN/5V OUT 3.3V IN/3.3V OUT
3.0
16
2.5
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.0
12
1.5
5V
8
1.0
3.3V
4
0.5
06577-016
0
5
10 15 DATA RATE (Mbps)
20
25
0
5
10 15 DATA RATE (Mbps)
20
25
Figure 13. Typical ICH Supply Current per Forward Data Channel (15 pF Output Load)
Figure 16. Typical IISO(D) Dynamic Supply Current per Output (15 pF Output Load)
Rev. PrA | Page 12 of 21
06577-118
0
0
06577-119
0
06577-017
0
Preliminary Technical Data TERMINOLOGY
IDD1(Q) IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2 Mbps, requiring no additional dynamic supply current. IDDIO(Q) reflects the minimum current operating condition. IDD1(D) IDD1(D) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load. IDD1(MAX) IDD1(MAX) is the input current under full dynamic and VISO load conditions. tPHL Propagation Delay tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal.
ADuM5400
tPLH Propagation Delay tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. Propagation Delay Skew (tPSK) tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Channel-to-Channel Matching Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. Minimum Pulse Width The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Maximum Data Rate The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
Rev. PrA | Page 13 of 21
ADuM5400
APPLICATIONS INFORMATION
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM5400 works on principles that are common to most modern power supplies. It is a secondary side controller architecture with isolated pulsewidth modulation (PWM) feedback. VDD1 power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. Power transferred to the secondary side is rectified and regulated to either 3.3 V or 5 V. The secondary (VISO) side controller regulates the output by creating a PWM control signal that is sent to the primary (VDD1) side by a dedicated iCoupler data channel. The PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency. The ADuM5400 implements under voltage lockout (UVLO) with hysteresis on the VDD1 power input. This feature ensures that the converter does not go into oscillation due to noisy input power or slow power on ramp rates. A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise on chip due to short or erratic PWM pulses. Excess noise generated this way can cause data corruption, in some circumstances.
BYPASS < 2mm VDD1 GND1 VIA/VOA VIB/VOB VIC/VOC VIC/VOD GND1
Preliminary Technical Data
VISO GNDISO VOA/VIA VOB/VIB VOC/VIC VOD/VID GNDISO
06577-120
VSEL
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins, exceeding the Absolute Maximum Ratings specified in Table 8, thereby leading to latch-up and/or permanent damage. The ADuM5400 is a power device that dissipates about 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the PCB through the GND pins. If the devices are used at high ambient temperatures, care should be taken to provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 17 shows enlarged pads for Pin 8 and Pin 9. Large diameter vias should be implemented from the pad to the ground, and power planes should be used to reduce inductance. Multiple vias in the thermal pads can significantly reduce temperatures inside the chip. The dimensions of the expanded pads are left to the discretion of the designer and the available board space.
PC BOARD LAYOUT
The ADuM5400 digital isolator with 0.5 W isoPower integrated dc-to-dc converters requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (Figure 17). Note that a low ESR bypass capacitor is required between Pin 1 and Pin 2, as close to the chip pads as possible. The power supply section of the ADuM5400 uses a very high oscillator frequency to efficiently pass power through its chip scale transformers. In addition, normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. These are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0.1 F and 33 F for VDD1. The smaller capacitor must have a low ESR; for example, use of a ceramic capacitor is advised. Note that the total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. A bypass between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both common ground pins are connected together close to the package.
THERMAL ANALYSIS
The ADuM5400 part consists of four internal die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the die are treated as a thermal unit, with the highest junction temperature reflected in the JA from Table 3. The value of JA is based on measurements taken with the parts mounted on a JEDEC standard, four-layer board with fine width traces and still air. Under normal operating conditions, the ADuM5400 device operates at full load across the full temperature range without derating the output current. However, following the recommendations in the PC Board Layout section decreases thermal resistance to the PCB, allowing increased thermal margins in high ambient temperatures.
Rev. PrA | Page 14 of 21
Preliminary Technical Data
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see Figure 18). The propagation delay to a logic low output may differ from the propagation delay to a logic high.
INPUT (VIx) 50%
ADuM5400
The limitation on the ADuM5400 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3.3 V operating condition of the ADuM5400 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude of >1.0 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt)rn2; n = 1, 2, ... , N where: is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM5400, and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19.
100
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
tPLH
OUTPUT (VOx)
tPHL
50%
03786-018
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM5400 component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM540x components operating under the same conditions.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5400 component must, of necessity, operate at very high frequency to allow efficient power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, good RF design practices should be followed in layout of the PCB. See www.analog.com for the most current PCB layout recommendations specifically for the ADuM5400.
10
1
0.1
0.01
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit. This situation should occur in the ADuM5400 device only during power-up and power-down operations.
100k 10k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 19. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing threshold of the decoder.
Rev. PrA | Page 15 of 21
06577-019
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
0.001 1k
ADuM5400
The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM5400 transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 20, the ADuM5400 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example, a 0.5 kA current would need to be placed 5 mm away from the ADuM5400 to affect component operation.
1k
MAXIMUM ALLOWABLE CURRENT (kA)
Preliminary Technical Data
Dynamic I/O current is consumed only when operating a channel at speeds higher than the refresh rate of fr. The dynamic current of each channel is determined by its data rate. Figure 13 shows the current for a channel in the forward direction, meaning that the input is on the VDD1 side of the part. Figure 14 shows the current for a channel in the reverse direction, meaning that the input is on the VISO side of the part. Both figures assume a typical 15 pF load. The following relationship allows the total IDD1 current to be calculated: IDD1 = (IISO x VISO)/(E x VDD1) + ICHn; n = 1 to 4 (1) where: IDD1 is the total supply input current. ICHn is the current drawn by a single channel determined from Figure 13 or Figure 14, depending on channel direction. IISO is the current drawn by the secondary side external load. E is the power supply efficiency at 100 mA load from Figure 5 at the VISO and VDD1 condition of interest. The maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. IISO(LOAD) = IISO(MAX) - IISO(D)n; n = 1 to 4 (2) where: IISO(LOAD) is the current available to supply an external secondary side load. IISO(MAX) is the maximum external secondary side load current available at VISO. IISO(D)n is the dynamic load current drawn from VISO by an input or output channel, as shown in Figure 15 and Figure 16. The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of IDD1 and IISO(LOAD).
DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 20. Maximum Allowable Current for Various Current-to- ADuM5400 Spacings
Note that in combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler data channels, as well as to the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary I/O channels cannot be determined separately. All of these quiescent power demands have been combined into the IDD1(Q) current, as shown in Figure 21. The total IDD1 supply current is equal to the sum of the quiescent operating current; the dynamic current, IDD1(D), demanded by the I/O channels; and any external IISO load.
IDD1(Q) IDD1(D) CONVERTER PRIMARY E CONVERTER SECONDARY IISO
IDDP(D)
IISO(D)
PRIMARY DATA I/O 4CH
SECONDARY DATA I/O 4CH
06577-024
Figure 21. Power Consumption Within the ADuM5400
Rev. PrA | Page 16 of 21
06577-020
0.01
Preliminary Technical Data
POWER CONSIDERATIONS
The ADuM5400 power input, the data input channels on the primary side, and the data input channels on the secondary side are all protected from premature operation by UVLO circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive, and all input channel drivers and refresh circuits are idle. Outputs are held in a low state. This is to prevent transmission of undefined states during power-up and powerdown operations. During application of power to VDD1, the primary side circuitry is held idle until the UVLO preset voltage is reached. At that time, the data channels are initialized to their default low output state until they receive data pulses from the secondary side. The primary side input channels sample the input and send a pulse to the inactive secondary output. The secondary side converter begins to accept power from the primary, and the VISO voltage starts to rise. When the secondary side UVLO is reached, the secondary side outputs are initialized to their default low state until data, either a transition or a dc refresh pulse, is received from the corresponding primary side input. It can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid one propagation delay after the secondary side becomes active. Because the rate of charge of the secondary side is dependent on loading conditions, input voltage, and output voltage level selected, care should be taken in the design to allow the converter to stabilize before valid data is required. When power is removed from VDD1, the primary side converter and coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side hold the last state that they received from the primary until either the UVLO level is reached and the outputs are placed in their default low state, or the outputs detect a lack of activity from the inputs and the outputs are set to their default value before the secondary power reaches UVLO.
ADuM5400
for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. The values shown in Table 9 summarize the peak voltages for 50 years of service life in several operating conditions. In many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. Operation at working voltages higher than the service life voltage listed leads to premature insulation failure. The insulation lifetime of the ADuM5400 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 22, Figure 23, and Figure 24 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. A 50-year operating lifetime under the bipolar ac condition determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 9 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 23 or Figure 24 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 9.
RATED PEAK VOLTAGE 0V
05007-021
Figure 22. Bipolar AC Waveform
RATED PEAK VOLTAGE
05007-023
0V
Figure 23. DC Waveform
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. Analog Devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM5400. Accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. Acceleration factors
RATED PEAK VOLTAGE
0V NOTES: 1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE WAVEFORM VARYING BETWEEN 0 AND SOME LIMITING VALUE. THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE VOLTAGE CANNOT CROSS 0V.
Figure 24. Unipolar AC Waveform
Rev. PrA | Page 17 of 21
05007-022
ADuM5400
OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
Preliminary Technical Data
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 25. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensiosn shown in millimeters and (inches)
ORDERING GUIDE
Model ADUM5400ARWZ1, 2 ADuM5400CRWZ1, 2
1 2
Number of Inputs, VDD1 Side 4 4
Number of Inputs, VISO Side 0 0
Maximum Data Rate (Mbps) 1 25
Maximum Propagation Delay, 5 V (ns) 100 60
Maximum Pulse Width Distortion (ns) 40 6
Temperature Range (C) -40 to +105 -40 to +105
032707-B
Package Description 16-Lead SOIC_W 16-Lead SOIC_W
Package Option RW-16 RW-16
Tape and reel are available. The addition of an RL suffix designates a 13" (1,000 units) tape and reel option. Z = RoHS Compliant Part.
Rev. PrA | Page 18 of 21
Preliminary Technical Data NOTES
ADuM5400
Rev. PrA | Page 19 of 21
ADuM5400
NOTES
Preliminary Technical Data
Rev. PrA | Page 20 of 21
Preliminary Technical Data NOTES
ADuM5400
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06577-0-5/08(PrA)
Rev. PrA | Page 21 of 21

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